Embodiments of the present invention relate to power management for devices coupled via an interconnect, and more particularly to power management via entry and control of an idle period.
High performance serial-based interconnect or link technologies such as Peripheral Component Interconnect (PCI) Express™ (PCIe™) links based on the PCI Express™ Specification Base Specification version 1.1 (published Mar. 28, 2005) (hereafter the PCIe™ Specification) are being adopted in greater numbers of systems. PCIe™ links are point-to-point serial interconnects with N differential pairs intended for data transmission with either sideband clock forwarding or an embedded clock provided in each direction. Clock synchronization and data recovery requirements significantly influence the exit latencies of low power state exit and thus impact the effective use of low power states if the serial link always has to be armed for asynchronous bus master traffic. For example, a phase-locked loop (PLL) and a platform reference clock remain energized in the ready state even in the absence of traffic activities. This has a direct and negative consequence on the average power consumption of both upstream (i.e., platform-based) device and downstream (i.e., peripherally-attached) device coupled to the link. As an example, the upstream device may be a chipset component of the platform, while the downstream device may be a wireless adapter.
In the PCIe™ Specification, various power saving states are provided for a link (i.e., an interface) of a serial interconnect. Specifically, the specification describes the presence of link states L0, L0s, L1, L2 and L3. The L0 state corresponds to link on and the L2 and L3 states correspond to link off (with the difference being that auxiliary power is present in the L2 state), while the L0, state provides for a low-resume standby latency state, and the L1 state corresponds to a low power standby state. These low power states may be achieved via the Active Status Power Management (ASPM) capability of a PCIe™ interface, which enables an endpoint device to request entry into a low power state. Per ASPM, the endpoint device is the only device permitted to request entry into the low power state, as the endpoint device has an understanding of the activities that it performs.
However, this rationale is not applicable to all devices coupled via a serial link such as a PCIe™ link. Furthermore, entry into a low power state does not provide any indication of an amount of time in which the state will be maintained. Accordingly, platform resources to which an endpoint device is coupled, e.g., a chipset and other such components oftentimes perform no power management as they are unaware of the length of the low power state. Furthermore, existing power management capabilities tend to ready the link for asynchronously-initiated traffic and thus provide limited power management opportunities. Accordingly, present mechanisms do not provide flexibility in entering and exiting low power states of devices coupled by links such as serial interconnects, nor do these states provide for aggressive power management of either endpoint devices or a platform to which such devices are coupled.